PART |
Description |
Maker |
W9412G6JH W9412G6JH-5 |
2M ?4 BANKS ?16 BITS DDR SDRAM Double Data Rate architecture; two data transfers per clock cycle
|
Winbond
|
CS433408 CS4338-KSZ CS4338-DSZ CS4339-KSZ |
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter D/A Converter (D-A) IC; Resolution (Bits):24; Update Rate:96kSPS; No. of DACs:2; Data Interface:Serial; Package/Case:8-SOIC; Interface Type:Serial; Leaded Process Compatible:No; No. of Bits:18; Operating Temp. Max:70 C RoHS Compliant: Yes
|
CIRRUS LOGIC INC
|
EA2-3SNU EA2-6SNP EA2-6SNU EA2-5SNJ EA2-5SNP EA2-5 |
COMPACT AND LIGHTWEIGHT 小巧轻便 CONNECTOR ACCESSORY A/D Converter (A-D) IC; Resolution (Bits):16; Sample Rate:4kSPS; Input Channels Per ADC:1; DNL :0.5LSB; Data Interface:Serial; Package/Case:20-DIP; Interface Type:Serial; Leaded Process Compatible:No; No. of Bits:16 RoHS Compliant: No Driver IC; Package/Case:28-SSOP; Supply Voltage Max:5V; Leaded Process Compatible:Yes; Number of Channels:3; Operating Temp. Max:70 C; Operating Temp. Min:-10 C; Frequency:20GHz; Interface Type:Serial A/D Converter (A-D) IC; Resolution (Bits):24; ADC Sample Rate:192kSPS; Input Channels Per ADC:6; Input Channel Type:Differential Inputs; Data Interface:Serial; Package/Case:48-LQFP
|
NEC, Corp. NEC Corp. NEC[NEC]
|
IDT5T9050PGI IDT5T9050 |
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERJR 2.5V的单数据传输速率1:5时钟缓冲器TERABUFFER⑩JR 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR 2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
|
Integrated Device Technology, Inc. IDT[Integrated Device Technology]
|
STEVAL-IKR002V1 |
SPIRIT1 - Low Data Rate Transceiver - 169 MHz - FULL KIT
|
ST Microelectronics
|
STEVAL-IKR001V2D |
SPIRIT1 - Low Data Rate Transceiver - 315 MHz - DAUGHTER BOARD
|
ST Microelectronics
|
K4D28163HD |
2M x 16Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
1064111050 |
QSFP to QSFP Fourteen Data Rate PSM4 Active Optical Cable, 56 Gbps Data Rate
|
Molex Electronics Ltd.
|
M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|